Wireless communication systems employ power amplifiers for increasing the power of radio frequency (RF) signals. In a wireless communication system, a power amplifier forms a portion of the last stage in a transmission chain before provision of the amplified signal to an antenna for radiation over the air interface. High gain, high linearity, stability, and a high level of power-added efficiency are characteristics of a desirable amplifier in such a wireless communication system.
In general, a power amplifier operates at maximum power efficiency when the power amplifier transmits close to saturated power. However, power efficiency tends to worsen as output power decreases. Recently, the Doherty amplifier architecture has been the focus of attention not only for base stations but also for mobile terminals because of the architecture's high power-added efficiency over a wide power dynamic range.
Put simply, a conventional two-way Doherty amplifier includes a signal splitter, parallel-coupled carrier and peaking amplifiers, and a combining node coupled to a load. The signal splitter divides an input RF signal into two RF signals with equal or unequal power, applies a phase shift to one or both of the two RF signals to achieve about a 90 degree phase difference between the signals, and provides the two RF signals to the carrier and peaking amplifiers. When the input RF signal power level is relatively low, only the carrier amplifier actively amplifies its received signal to produce an amplified output signal, which is provided to the load. At a given input signal power threshold, the peaking amplifier begins actively amplifying its received signal, and the carrier and peaking amplifier output RF signals are combined, in phase, at the combining node and provided to the load. As the input RF signal power level continues to increase, the peaking amplifier output signal level also increases up to a full-power output condition. Doherty amplifier operation at power levels below the full-power output condition is referred to as “back-off operation.”
An impedance inverter and Doherty load modulation line (referred to simply herein as an “impedance inverter line”) is coupled between the carrier and peaking amplifier outputs and the signal combiner. The impedance inverter line causes the impedance seen at the output of the carrier amplifier to reduce when the current from the peaking amplifier is injected into the load. The optimum efficiency output impedance of the amplifier during back-off operation is commonly referred to as Zmod, and the length of the impedance inverter line has a significant impact on the overall performance of the Doherty amplifier by setting a Zmod condition during back-off operation. To ensure that the output RF signals from the carrier and peaking amplifiers are combined in phase at the combining node, the electrical length of the impedance inverter line should be as close as possible to an odd multiple of 90 degrees, such as about 90 degrees (λ/4) or 270 degrees (3λ/4), where λ is the center frequency of operation of the amplifier.
The high efficiency of the Doherty amplifier makes the architecture desirable for current and next-generation wireless systems. However, with the increasing desire for system miniaturization, the architecture presents challenges in terms of semiconductor package design. In particular, Doherty amplifiers implemented in integrated packages often have stringent size constraints that dictate the potential physical length of an impedance inverter line. Further, it is desirable from a loss standpoint to make impedance inverter lines as compact as possible. However, there is an inherent tradeoff between impedance inverter line compactness and the ease of designing Doherty amplifiers with optimized performance.